Method and apparatus for enhancing noise tolerance in dynamic silicon-on-insulator logic gates
US6326814A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2000 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Mar 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3872
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for enhancing noise tolerance in dynamic Silicon-On-Insulator (SOI) logic gates improves the performance of dynamic gates using SOI technology. In particular implementations of logic, the logic inputs can be used to enable a pull-up chain constructed from a plurality of transistors. This pull-up chain holds the preset voltage on the summing node of the dynamic logic gate while the logic inputs are in a combination where parasitic bipolar transistors in the input logic chains conduct. The pull-up chain prevents spurious operation of the logic gate due to the conduction of the parasitic bipolar transistors. The pull-up also prevents spurious operation due to charge sharing that occurs when a device in the logic chain is enabled while another device is disabled. The charge sharing occurs due to charging the diffusion capacitance of the device which is disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.