Semiconductor device and a method of operation the same
US6327182A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1999 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Dec 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a memory array includes memory cells (101-104), a word line (42), a first bit line (68), and a second bit line (76). Within the memory array, the first and second bit lines (68 and 76) lie at different elevations above the word line (42). Local interconnects (58) are electrically connected to the first bit line (68) and some of the current carrying electrodes (48) in the memory array. The local interconnects (58) allow offset connections to be made. For floating gate memory cells (101-104) in a NOR-type memory array architecture, programming and erasing can be performed using a relatively uniform bias between the source and drain regions (46 and 48) of a memory cell (101) to be programmed without significantly disturbing data in adjacent floating gate memory cells (102-104).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.