James D. Burnett
60Patents
14h-index
58Co-inventors
87Inventor score
Filing activity: Apr 8, 1977 → Aug 14, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6861689B2 | One transistor DRAM cell structure and method for forming | Physics | 150 | Expired |
| US6714436B1 | Write operation for capacitorless RAM | Electricity | 130 | Expired |
| US7238990B2 | Interlayer dielectric under stress for an integrated circuit | Emerging Cross-Sectional Technologies | 39 | Expired |
| US7285832B2 | Multiport single transistor bit cell | Emerging Cross-Sectional Technologies | 32 | Expired |
| US5541132A | Insulated gate semiconductor device and method of manufacture | Emerging Cross-Sectional Technologies | 32 | Expired |
| US7085175B2 | Word line driver circuit for a static random access memory and method therefor | Physics | 30 | Expired |
| US7292495B1 | Integrated circuit having a memory with low voltage read/write operation | Physics | 25 | Active |
| US4141322A | Insecticidal collar for animals | Human Necessities | 23 | Expired |
| US7709303B2 | Process for forming an electronic device including a fin-type structure | Electricity | 20 | Active |
| US7754560B2 | Integrated circuit using FinFETs and having a static random access memory (SRAM) | Electricity | 19 | Active |
| US7352631B2 | Methods for programming a floating body nonvolatile memory | Electricity | 19 | Expired |
| US7800959B2 | Memory having self-timed bit line boost circuit and method therefor | Physics | 17 | Active |
| US7238555B2 | Single transistor memory cell with reduced programming voltages | Physics | 16 | Expired |
| US7733711B2 | Circuit and method for optimizing memory sense amplifier timing | Physics | 14 | Active |
| US6327182A | Semiconductor device and a method of operation the same | Physics | 14 | Expired |
| US7542369B2 | Integrated circuit having a memory with low voltage read/write operation | Physics | 13 | Active |
| US7195983B2 | Programming, erasing, and reading structure for an NVM cell | Electricity | 13 | Expired |
| US8947970B2 | Word line driver circuits and methods for SRAM bit cell with reduced bit line pre-charge voltage | Physics | 11 | Active |
| US7452768B2 | Multiple device types including an inverted-T channel transistor and method therefor | Electricity | 11 | Expired |
| US6760270B2 | Erase of a non-volatile memory | Physics | 9 | Expired |
| US8156357B2 | Voltage-based memory size scaling in a data processing system | Emerging Cross-Sectional Technologies | 9 | Active |
| US7483327B2 | Apparatus and method for adjusting an operating parameter of an integrated circuit | Emerging Cross-Sectional Technologies | 9 | Active |
| US7968394B2 | Transistor with immersed contacts and methods of forming thereof | Electricity | 8 | Active |
| US7414877B2 | Electronic device including a static-random-access memory cell and a process of forming the electronic device | Electricity | 8 | Active |
| US7336533B2 | Electronic device and method for operating a memory circuit | Physics | 8 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.