Complementary differential input buffer for a semiconductor memory device
US6327190A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2000 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Mar 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input buffer of a semiconductor memory device includes a first differential amplifying portion including a first MOS transistor for receiving a first external input signal and a second MOS transistor for receiving a second external input signal. The voltage difference between the first and second external input signals is amplified and output as a first intermediate output voltage. A second differential amplifying portion includes a third MOS transistor for receiving the first external input signal and a fourth MOS transistor for receiving the second external input signal. The voltage difference between the first and second external input signals are amplified and output as a second intermediate output voltage. The first intermediate output of the first amplifying portion is combined with the second intermediate output of the second amplifying portion and the combined result is output as an output signal. The input buffer is less susceptible to fluctuations in ground and supply voltage levels due to noise, and the set-up time and hold time margins of the output signal are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.