Structure and method of a column redundancy memory
US6327197A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2000 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Sep 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture is disclosed that employs multiple column redundancies which provide multiple options for replacing a defective global odd or even bit line. Each column memory has two multiplexers, one for selecting a global odd bit line and another for selecting a global even bit line. Two or more column redundancies are coupled to each of the multiplexer in the column memory. In a first embodiment, the global odd and even bit lines are connected through odd and even sense amps in a regular column. In a second embodiment, the global odd bit line in a regular column connects through odd sense amps, while the global even bit line in the regular column connects through even sense amps. In a third embodiment, two or more sets of redundancy columns are commonly coupled to a left adjacent regular column and a right adjacent regular column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.