Process, voltage, temperature independent switched delay compensation scheme
US6327318A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1998 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Jun 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.