Method and apparatus for board model correction
US6327545A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1998 |
| Grant date | Dec 4, 2001 |
| Priority date | — |
| Expiry date | Oct 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2846
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.