Method for producing high quality heteroepitaxial growth using stress engineering and innovative substrates
US6329063A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1998 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Dec 11, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/12681
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing a stress-engineered substrate includes selecting first and second materials for forming the substrate. An epitaxial material for forming a heteroepitaxial layer is then selected. If the lattice constant of the heteroepitaxial layer (a.sub.epi) is greater than that (a.sub.sub) of the immediate substrate layer the epitaxial layer is deposited on, then the epitaxial layer is kept under "compressive stress" (negative stress) at all temperatures of concern. On the other hand, if the lattice constant of the heteroepitaxial layer (a.sub.epi) is less than that (a.sub.sub) of the immediate substrate layer the epitaxial layer is deposited on, then the epitaxial layer is kept under "tensile stress" (positive stress). The temperatures of concern range from the annealing temperature to the lowest temperature where dislocations are still mobile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.