Method for patterning dual damascene interconnects using a sacrificial light absorbing material
US6329118A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Oct 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method of forming an integrated circuit, which includes forming a conductive layer on a substrate, then forming a dielectric layer on the conductive layer. After forming the dielectric layer, a layer of photoresist is patterned to define a region to be etched. A first etched region is then formed by removing a first portion of the dielectric layer. That first etched region is filled with a preferably light absorbing sacrificial material having dry etch properties similar to those of the dielectric layer. A second etched region is then formed by removing the sacrificial material and a second portion of the dielectric layer. This improved method may be used to make an integrated circuit that includes a dual damascene interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.