Method for making split gate flash memory cells with high coupling efficiency
US6329248A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2000 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Mar 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A process for making split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an interpoly dielectric layer. This process includes the steps of: (a) forming a first dielectric layer having a trench region on a substrate; (b) forming a tunnel oxide layer in the trench region; (c) forming a first polysilicon layer covering the first dielectric layer and the tunnel oxide layer; (d) applying an anisotropic etching technique on the first polysilicon layer to form a pair of opposing polysilicon sidewall spacers on the sidewalls which will eventually become floating gates; (e) depositing an inter-poly dielectric layer on the polysilicon sidewall spacers and the tunnel oxide layer; (f) filling the channel area between the pair of polysilicon sidewall spacers with a second polysilicon layer; (g) planarizing the second polysilicon layer so that relative to the first dielectric layer to form a control gate; (h) removing the first dielectric layer, capping the control gate and the floating gate with a final oxide layer, and forming source and drain regions in the substrate using ion implantation. The …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.