Method of forming self-aligned silicide in semiconductor device
US6329276A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Sep 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a semiconductor device fabrication method. In the method, a gate layer is formed on a semiconductor substrate and patterned to form a first resultant structure, a metal layer is formed on the first resultant structure, a capping layer is formed on the metal layer, a metal silicide is formed on the gate layer by heating the substrate at a first temperature, unreacted metal layer and first capping layer are removed to form a second resultant structure, a second capping layer is formed on the second resultant structure, and the substrate is heated at a second temperature higher than the first temperature. The second capping layer suppresses a silicidation rate in the secondary heat treatment, thereby allowing a silicide of a good morphology to be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.