Ja-Hum Ku
44Patents
11h-index
78Co-inventors
78Inventor score
Filing activity: Sep 29, 1998 → May 30, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9508727B2 | Integrated circuit device and method of manufacturing the same | Electricity | 35 | Active |
| US6383877B1 | Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer | Electricity | 30 | Expired |
| US7911001B2 | Methods for forming self-aligned dual stress liners for CMOS semiconductor devices | Electricity | 23 | Active |
| US6329276A | Method of forming self-aligned silicide in semiconductor device | Electricity | 22 | Expired |
| US6936528B2 | Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film | Electricity | 21 | Expired |
| US7084061B2 | Methods of fabricating a semiconductor device having MOS transistor with strained channel | Electricity | 18 | Expired |
| US7297584B2 | Methods of fabricating semiconductor devices having a dual stress liner | Electricity | 17 | Expired |
| US6624496B2 | Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer | Electricity | 17 | Expired |
| US7586175B2 | Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface | Electricity | 15 | Active |
| US7514354B2 | Methods for forming damascene wiring structures having line and plug conductors formed from different materials | Electricity | 15 | Expired |
| US7615432B2 | HDP/PECVD methods of fabricating stress nitride structures for field effect transistors | Electricity | 12 | Active |
| US7534678B2 | Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby | Electricity | 11 | Active |
| US6764961B2 | Method of forming a metal gate electrode | Electricity | 10 | Expired |
| US7781322B2 | Nickel alloy salicide transistor structure and method for manufacturing same | Electricity | 8 | Expired |
| US10014304B2 | Integrated circuit device and method of manufacturing the same | Electricity | 8 | Active |
| US7109104B2 | Methods of fabricating a semiconductor device having a metal gate pattern | Electricity | 8 | Expired |
| US6218690A | Transistor having reverse self-aligned structure | Electricity | 6 | Expired |
| US8016941B2 | Method and apparatus for manufacturing a semiconductor | Electricity | 6 | Active |
| US6960515B2 | Method of forming a metal gate | Electricity | 5 | Expired |
| US7232756B2 | Nickel salicide process with reduced dopant deactivation | Electricity | 5 | Expired |
| US7816271B2 | Methods for forming contacts for dual stress liner CMOS semiconductor devices | Electricity | 5 | Active |
| US6797559B2 | Method of fabricating semiconductor device having metal conducting layer | Electricity | 5 | Expired |
| US7598572B2 | Silicided polysilicon spacer for enhanced contact area | Electricity | 3 | Active |
| US7576407B2 | Devices and methods for constructing electrically programmable integrated fuses for low power applications | Electricity | 3 | Active |
| US8008177B2 | Method for fabricating semiconductor device using a nickel salicide process | Electricity | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.