Semiconductor memory device and manufacturing method thereof which make it possible to improve reliability of cell-capacitor and also to simplify the manufacturing processes
US6329683A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2000 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Dec 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In this DRAM, an SiO.sub.2 film for assuring the step coverage of cell-capacitor of cylinder type is left remained only in the peripheral circuit region. The capacitor upper electrode is formed extending from the memory cell array region to the peripheral circuit region. Since the capacitor upper electrode in the peripheral circuit region is disposed higher than the upper surface of the capacitor upper electrode which constitutes the cell-capacitor, this capacitor upper electrode in the peripheral circuit region is employed as a stopper for subsequently flattening the interlayer insulating film. Subsequently, the interlayer insulating film is employed as a mask for etching the capacitor upper electrode in the peripheral circuit region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.