Device for protection of sensitive gate dielectrics of advanced non-volatile memory devices from damage due to plasma charging
US6329691A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 13, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Dec 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
A protective circuit includes a pair of diodes to protect the gate dielectric of an insulated-gate semiconductor device from over-voltage conditions, such as can occur during plasma etch manufacturing processes. The diodes are either anode- or cathode-coupled, and are connected between the gate of the device and bulk ground. Because of their opposing polarities, one of the diodes is always reverse-biased regardless of whether a positive or negative control voltage is applied to the gate of the device. As a result, the protective circuit imposes no operational restrictions on normal control voltages. At the same time, the circuit limits any plasma-induced charge buildup that can arise during manufacturing. If the gate voltage rises, a first of the two diodes is reverse biased and prevents the protective circuit from conducting. When the gate voltage reaches the reverse breakdown voltage of the first diode (plus the small forward voltage drop of the second diode), both diodes begin to conduct. Any subsequent charge accumulation at the gate is drained off by the protective circuit. Similarly, if the magnitude of a negative gate voltage reaches the reverse breakdown voltage of the seco…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.