Cross-coupled dual rail dynamic logic circuit
US6329846A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2000 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Apr 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Logic functions using dual rail dynamic logic circuits are implemented by cross-coupling a pair shunt transistors to the outputs. Preferably, the precharge nodes provide input to the gates of respective inverter drivers, each inverter formed as a p-channel field-effect transistor (pFET) and an n-channel field-effect transistor (nFET). The circuit's logic functions discharge the precharge nodes to ground. Therefore, one of the precharge nodes discharges to ground, while the other retains its positive precharge. The inverter drivers drive the discharged precharge node high, while the precharge node which retains its original charge is driven low. The shunt transistors are nFETs which connect the outputs of the inverter drivers to ground. The gate of each shunt transistor is driven by the output of the opposite inverter driver. The output which is driven by a discharged precharge node is relatively immune from noise, since there is a path from the precharge node to ground through several open transistors. The output driven by the discharged precharge node will turn on the shunt transistor for the complementary output, bringing that output to the correct logic value even if noise is pr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.