Clock input buffer with noise suppression
US6329867A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Sep 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is designed with a delay circuit (300) coupled to receive a clock input signal (CLK) and a control signal (DFT). The control signal has a first logic state and a second logic state. The delay circuit produces a clock control signal (*CLK) at a first time in response to the first logic state and at a second time in response to the second logic state. A clock circuit (200) is coupled to receive the clock input signal and is enabled by the clock control signal. The clock circuit produces a first clock pulse signal having a predetermined width in response to a first transition of the clock input signal and produces a second clock pulse signal having the predetermined width in response to a second transition of the clock input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.