Inventor · Allen, TX, US

William C. Waldrop

32Patents
8h-index
18Co-inventors
72Inventor score

Filing activity: Sep 7, 1999 → Aug 18, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US6605969B2 Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers Electricity 61 Expired
US6549041B2 Scheme for delay locked loop reset protection Electricity 35 Expired
US6452431B1 Scheme for delay locked loop reset protection Electricity 20 Expired
US6885226B2 Programmable dual-drive strength output buffer with a shared boot circuit Electricity 17 Expired
US6693472B2 Method and circuit for adjusting the timing of output data based on an operational mode of output drivers Electricity 15 Expired
US6975149B2 Method and circuit for adjusting the timing of output data based on an operational mode of output drivers Electricity 15 Expired
US6819151B2 Method and circuit for adjusting the timing of output data based on an operational mode of output drivers Electricity 10 Expired
US6559690B2 Programmable dual drive strength output buffer with a shared boot circuit Electricity 8 Expired
US6329867A Clock input buffer with noise suppression Electricity 6 Expired
US7560956B2 Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals Physics 5 Expired
US7230457B2 Programmable dual drive strength output buffer with a shared boot circuit Electricity 3 Expired
US7915924B2 Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals Physics 3 Active
US10447267B1 Systems and methods for controlling semiconductor device wear Electricity 2 Active
US10783980B2 Methods for parity error synchronization and memory devices and systems employing the same Physics 1 Active
US10354717B1 Reduced shifter memory system Physics 1 Active
US11264078B2 Metastable resistant latch Physics 1 Active
US11487610B2 Methods for parity error alert timing interlock and memory devices and systems employing the same Physics 1 Active
US11417374B1 Reset speed modulation circuitry for a decision feedback equalizer of a memory device Physics 1 Active
US11145353B1 Centralized DFE reset generator for a memory device Electricity 1 Active
US10872658B2 Reduced shifter memory system Physics 0 Active
US7675324B2 Pre-driver logic Electricity 0 Active
US9479361B2 Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals Physics 0 Active
US12223999B2 Synchronous input buffer control using a write shifter Physics 0 Active
US11727979B2 Methods of reducing clock domain crossing timing violations, and related devices and systems Physics 0 Active
US7898294B2 Pre-driver logic Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.