Method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode
US6329874A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1998 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Sep 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Standby leakage reduction circuitry that uses boosted gate drive of a leakage control transistor during an active mode. A circuit block includes a first leakage control transistor coupled to receive a first supply voltage and coupled in series with an internal circuit block that performs a particular function. A gate drive circuit is included to apply a first boosted gate drive voltage to a gate of the first leakage control transistor during an active mode of the internal circuit block. The gate drive circuit furthers applies a standby gate voltage to the gate during a standby mode of the internal circuit block, the standby gate voltage to cause a gate to source voltage of the leakage control transistor to be reverse-biased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.