Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank
US6330636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1999 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Jan 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A double data rate ("DDR") synchronous dynamic random access memory ("SDRAM") device incorporating a static random access memory ("SRAM") cache per memory bank that provides effectively double peak data bandwidth, optimizes sustained bandwidth and improves bus efficiency as compared with conventional DDR SDRAM devices. The memory device disclosed provides effectively faster basic DRAM memory latency parameters, faster page "hit" latency, faster page "miss" latency and sustained bandwidth on random burst reads, faster read-to-write latency and write-to-read latency, hidden precharge, hidden bank activate latency, hidden refresh and hidden write precharge during a read "hit".
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.