Data receiver that performs synchronous data transfer with reference to memory module
US6330650A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1998 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Apr 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0996
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data receiver is incorporated in a controller which receives data from memory modules. The data transfer is provided with an S receiver and a D receiver. The S receiver is driven on the basis of first multiphase clocks and receives strobe signals. The D receiver is driven on the basis of outputs from the S receiver, which receives states of the strobe signals at the respective times, and the second multiphase clocks which lag the first multiphase clocks by a predetermined length of time. The D receiver receives data and transfers the same. The S receiver is controlled for burst data transfer such that the S receiver is set in an active state immediately before a strobe signal corresponding to a start item of burst data rises, and is set in an inactive state after a last item of the burst data is received. A multiphase clock generator is provided. The multiphase clock generator generates the first and second multiphase clocks which have predetermined phase differences and are equal in period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.