Method and apparatus for controlling power level during BIST
US6330681A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1998 |
| Grant date | Dec 11, 2001 |
| Priority date | — |
| Expiry date | Dec 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318552
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An improvement in a method of testing a digital circuit or system, having a plurality of scannable memory elements, in accordance with conventional BIST methods in which, at a reference clock, a test stimulus is shifted into the memory elements, the response of the elements is captured and the captured data is shifted out of the elements and analyzed, the improvement comprising controlling the average power consumption of the circuit during the test by suppressing clock pulses from the reference clock during phases of the test that do not require the maximum level of activity or in which the performance of the circuit is not to be evaluated; and, suppressing no clock pulses from the reference clock in phases of the test in which the performance of the circuit is to be evaluated, so that the conditions are substantially as those of normal mode of operation of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.