Method for manufacturing low power high efficiency non-volatile erasable programmable memory cell structure
US6331463A · kind A · utility
26Cited by
6References
26Claims
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Key dates
| Filing date | Jan 18, 1999 |
| Grant date | Dec 18, 2001 |
| Priority date | — |
| Expiry date | Jan 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
Abstract
A low power high efficiency non-volatile erasable programmable memory cell structure has a characteristic, distributed, floating gate structure comprising an assembly of independent crystalline silicon crystals. Each crystalline silicon crystal has a diameter of roughly between 10 .ANG. and 100 .ANG. and is separated from the other crystals by a distance greater than 50 .ANG..
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.