Method for forming SiGe bipolar transistor
US6333235A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2000 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Apr 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/021
Abstract
A method for fabricating bipolar transistor frequently used in high frequency circuit is disclosed herein. The foregoing method includes the following steps. First, a first oxide layer is formed on a p-type substrate, followed by developing a first photoresist pattern on the first oxide layer. A first, doped region is formed in the exposed substrate by a first implanting step. The first doped region comprises a n+ buried layer. Stripping of the first photoresist pattern, and annealing of the n+ buried layer follow. Removal of the first oxide layer to expose the n+ buried layer and a portion of the p-type substrate follows thereafter. These steps are followed by growing a first epitaxial layer on the n+ buried layer and a portion of the substrate, then a second epitaxial layer is formed on the first epitaxial layer. The first epitaxial layer is made of epitaxial n-type silicon, and the second epitaxial layer is made of in situ epitaxial p-type SiGe. Next, a plurality of first and second trench isolation are formed. A gate oxide layer is formed and the extrinsic base is formed in the second epitaxial layer. A polysilicon emitter pattern is formed and is connected to the intrinsic bas…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.