Method of manufacturing a semiconductor device
US6333258A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2000 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Mar 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method for forming a dual damascene structure in which the effective permittivity of an inter-layer insulating film is lowered without an etching mask for forming a contact hole, which is otherwise formed in the inter-layer insulating film. The manufacturing method comprises the step of forming an inorganic film to serve as an etching mask, on the inter-layer insulating film; the step of forming a first opening pattern for forming a wiring groove, in an upper part of the inorganic film; and the step of forming a second opening pattern for forming a contact hole, so as to coincide with the first opening pattern at least partially. Further, the contact hole is formed in the inter-layer insulating film by employing an etching mask made of the inorganic film, the inorganic film is etched into a state where only a third opening pattern obtained by transferring the first opening pattern is formed, and a wiring groove is formed in the inter-layer insulating film by employing the resulting inorganic film as the etching mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.