Method for forming silicide
US6333262A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2000 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Aug 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming silicide on a semiconductor wafer. The semiconductor wafer includes a doped silicon layer on a predetermined area of the semiconductor wafer, a metal layer positioned on the doped silicon layer, and a barrier layer covering the metal layer. A first rapid thermal processing (RTP) step is performed to make portions of the metal layer react with silicon inside the doped silicon layer so as to form a transitional silicide. The barrier layer and the portions of the metal layer that have not reacted with silicon are then removed. A dielectric layer is formed on the transitional silicide. Finally, a second rapid thermal processing (RTP) step is performed to make the transitional silicide react with portions of the doped silicon layer so as to form the silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.