Clocked logic gate circuit
US6333645A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2000 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Sep 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1738
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.