Processor coupled by visible register set to modular coprocessor including integrated multimedia unit
US6334180A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 2000 |
| Grant date | Dec 25, 2001 |
| Priority date | — |
| Expiry date | Oct 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A coprocessor coupled to a hardware processor and capable of performing multimedia operations is provided. The coprocessor includes an instruction fetch and decode unit which is coupled to a plurality of execution units including an integer execution unit and a multimedia execution unit. The coprocessor includes a superscalar architecture and each of the execution units includes a plurality of pipelined stages. Accordingly, the multimedia execution unit has several integer execution units which can be executed in parallel for improved multimedia performance. A visible register set is coupled to the integer execution unit for receiving operands to initialize operation of the coprocessor. Further, a first register file is coupled to the multimedia execution unit and a second register file is coupled to the integer execution unit. A memory bus coupled to memory and the integer execution unit is used for accessing data and multimedia applications in memory as indicated by values in the visible register set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.