Integrated dielectric and method

US6335238B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Sunil V. Hanttangady · McKinney, US
• Robert M. Wallace · Richardson, US
• Bruce E. Gnade · Rowlett, US
• Yasutoshi Okuno · Hsinchu, TW

Key dates

• Filing date: May 5, 1998
• Grant date: Jan 1, 2002
• Expiry date: May 5, 2018

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/931
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer. Applications for high permittivity memory cells and gate dielectrics are disclosed. This method has steps of providing a partially completed integrated circuit having a semiconductor layer substantially comprising silicon, where the layer has an exposed face. The method also includes forming an ultra-thin SiC reaction barrier at the exposed face, and depositing a high permittivity storage dielectric on the SiC reaction barrier. Typically, the SiC reaction barrier is less then 25 å thick, preferably one or two monolayers of SiC.