Semiconductor device having stress reducing laminate and method for manufacturing the same
US6335567B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1999 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Jul 8, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a stress reducing laminate. Grooves are formed on the surface of a material layer selected from a multilayer structure of the semiconductor device, for example, a conductive layer. The cross sections of the grooves are semicircular or semi-elliptic. The stress applied to the conductive layer having the grooves is divided into a vertical component and a horizontal component with respect to the surface of the conductive layer. Accordingly, the stress applied vertically to the conductive layer is reduced, making it is possible to prevent the conductive layer from cracking due to stress and to reduce the stress transmitted to material layers under the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.