Semiconductor integrated circuit device, method of investigating cause of failure occurring in semiconductor integrated circuit device and method of verifying operation of semiconductor integrated circuit device
US6335894B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2000 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Oct 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.