System and method for merging multiple outstanding load miss instructions
US6336168B1 · kind B1 · utility
30Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.