Delay optimized mapping for programmable gate arrays with multiple sized lookup tables
US6336208B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1999 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process for mapping logic nodes to a plurality of sizes of lookup tables in a programmable gate array. A node and its predecessor nodes are selectively collapsed into a first single node as a function of delay factors associated with the plurality of sizes of lookup tables and a maximum of delay factors associated with the predecessor nodes. If a cut-size associated with the first single node is less than or equal to one of the sizes of lookup tables, the one size is selected to implement the first single node. If a lookup table size was not selected for the first single node, the node and its predecessor nodes are selectively collapsed into a second single node as a function of the delay factors and the maximum delay factor increased by a selected value. If a cut-size associated with the second single nodes is less than or equal to one of the sizes of lookup tables, the one size is selected to implement the second single node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.