Method for integration of integrated circuit devices
US6337265B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2000 |
| Grant date | Jan 8, 2002 |
| Priority date | — |
| Expiry date | Sep 1, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/544
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for integration of integrated circuit devices includes providing an array of first devices including dummy devices on a first chip; providing an array of contacts on a second chip; flip-chip bonding the first device to the contacts; filing the voids between the two interstitially of the first devices with an underfill; masking the first devices leaving exposed selected dummy devices; removing the dummy devices leaving an array of holes with contacts; providing a spaced array of second devices on a third chip matching the array of holes; flip-chip bonding the second devices to the contacts in the holes; and filling the voids between the chips associated with second devices with an underfill.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.