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US6338123B2 · kind B2 · utility

15Cited by
2References
16Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 31, 1999
Grant dateJan 8, 2002
Priority date
Expiry dateMar 31, 2019

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F12/0822
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method and structure for a system for maintaining coherence of cache lines in a shared memory multiplexor system comprises a system area network and a plurality of compute nodes connected to the system area network. Each of the computer nodes includes a local main memory, a local shared cache and a local coherence controller and computer nodes external to a given compute node include external shared caches and the coherence controller includes shadow directories, each corresponding to one of the external shared caches. Each of the shadow directories includes state information of the local main memory cached in the external shared caches. The shadow directories include only state information of the local main memory cached in the external shared caches.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.