Method to fabricate embedded DRAM with salicide logic cell structure
US6338993B1 · kind B1 · utility
16Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1999 |
| Grant date | Jan 15, 2002 |
| Priority date | — |
| Expiry date | Aug 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
Abstract
A method for forming salicide on the peripheral logic region of the embedded DRAM without using a salicide block mask layer to protect the memory cell region of the embedded DRAM and without oxide wet dip to prevent oxide loss in the field oxide is disclosed. Additionally, the landing plug process in the memory cell region is performed by a self-aligned contact (SAC) etching process with a silicon nitride layer as an etching protective layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.