Method of fabricating a non-volatile semiconductor device
US6339015B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2000 |
| Grant date | Jan 15, 2002 |
| Priority date | — |
| Expiry date | May 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate. The two adjacent spikes are formed by first forming spacers on sidewalls of the opening to reduce a width thereof; filling the reduced opening with a mask plug; removing the sidewalls; and etching the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.