Ferroelectric field effect transistor, memory utilizing same, and method of operating same
US6339238B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1999 |
| Grant date | Jan 15, 2002 |
| Priority date | — |
| Expiry date | Jun 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric non-volatile memory in which each memory cell consists of a single electronic element, a ferroelectric FET. The FET includes a source, drain, gate and substrate. A cell is selected for writing or reading by application of bias voltages to the source, drain, gate or substrate. A gate voltage equal to one truth table logic value and a drain voltage equal to another truth table logic value are applied via a row decoder, and a substrate bias equal to a third truth table logic value is applied via a column decoder to write to the memory a resultant Ids logic state, which can be non-destructively read by placing a voltage across the source and drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.