Optimized floating P+ region photodiode for a CMOS image sensor
US6339248B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1999 |
| Grant date | Jan 15, 2002 |
| Priority date | — |
| Expiry date | Nov 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/803
Abstract
A photodiode with an optimized floating P+ region for a CMOS image sensor. The photodiode is constructed with a P+/Nwell/Psub structure. The Nwell/Psub junction of the photodiode acts as a deep junction photodiode which offers high sensitivity. The P+ floating region passivates the silicon surface to reduce dark currents. Unlike a traditional pinned photodiode structure, the P+ region in the present invention is not connected to the Pwell or Psub regions, thus making the P+ region floating. This avoids the addition of extra capacitance to the cell. The photodiode may be included as part of an active pixel sensor cell, the layout of which is fully compatible with the standard CMOS fabrication process. This type of active pixel sensor cell includes the photodiode, and may be configured with a three transistor configuration for reading out the photodiode signals. Examples of other configurations that the photodiode can be used with include two transistors, four transistors, log scale, as well as its ability to be used in a passive pixel implementation. Also, an additional optional N type layer can be introduced in between the P+ region and Nwell to fine tune the junction profile for s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.