Charge retention lifetime evaluation method for nonvolatile semiconductor memory
US6339557B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2000 |
| Grant date | Jan 15, 2002 |
| Priority date | — |
| Expiry date | May 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a nonvolatile semiconductor memory, a floating gate electrode is disposed above a silicon substrate between source and drain regions, through a tunnel film, and a control gate electrode is disposed above the floating gate electrode through an insulating film. The substrate is grounded and at least two negative voltages are respectively applied to the control gate electrode, so that a voltage is applied to the tunnel film. In these cases, charge retention properties are evaluated. The voltages applied to the control gate electrode are controlled so that the voltage applied to the tunnel film does not exceed a voltage applied to the tunnel film during a memory operation. A charge retention property when no voltage is applied across the control gate electrode and the substrate, i.e., when no voltage is externally applied to the tunnel film, is estimated by the charge retention properties when the two voltages are applied to the control gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.