Method for forming metal line in semiconductor device
US6340636B1 · kind B1 · utility
1Cited by
8References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1999 |
| Grant date | Jan 22, 2002 |
| Priority date | — |
| Expiry date | Oct 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a metal line in a semiconductor device, in which a resolution is improved for securing a design rule and minimizing a difference of critical dimensions, including the steps of (1) forming a first insulating film and a second insulating film on a substrate, (2) etching the second insulating film to form a second insulating film pattern, (3) depositing a third insulating film on the second insulating film pattern, (4) removing the second insulating film pattern, and (5) forming a metal line layer in a region having the second insulating film pattern removed therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.