Method for forming a passivation layer on copper conductive elements
US6340638B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Jan 22, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76886
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a passivation layer on at least one copper conductive element in a semiconductor structure and the devices formed are described. In the method, after a top surface of a semiconductor device that contains copper conductors embedded in an insulating layer is first planarized by a chemical mechanical polishing method, an etching process is conducted to create a stepped or corrugated surface between the surface of the copper conductor and the surface of the insulating layer, so that when a passivation layer is later deposited on top of the semiconductor structure, the same stepped or corrugated surface is reproduced in the passivation layer and thus providing a mechanical interlock between the passivation layer and the copper conductor for preventing adhesion failure or peeling of the passivation layer from the surface of the semiconductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.