Dynamic random access memory in switch MOSFETs between sense amplifiers and bit lines
US6341088B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Jan 22, 2002 |
| Priority date | — |
| Expiry date | Dec 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Switch MOSFETs are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines. After signal voltages are read out by selecting operations of word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. This turns on the switch MOSFETs thereby setting sense nodes to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned to the select level in response to the selecting operation of the column select circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.