SOI array sense and write margin qualification
US6341093B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Jan 22, 2002 |
| Priority date | — |
| Expiry date | Jun 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.