Apparatus and method for implementing a snoop bus protocol without snoop-in and snoop-out logic
US6341337B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 1998 |
| Grant date | Jan 22, 2002 |
| Priority date | — |
| Expiry date | Jan 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a method and apparatus that implements a snoop protocol in a multiprocessor system without the use of snoop-in and snoop-out logic units. The multiprocessor system includes a number of nodes connected by a bus operated in accordance with a snoop protocol and the MOSI cache coherency protocol. Each node includes a cache memory and a main memory unit including a shared memory region that is distributed in one or more of the cache memories of the nodes in the system. Each node includes a memory access unit having an export cache that stores identifiers associated with data blocks that have been modified by another node. Each data block in the main memory unit is associated with a state bit that indicates whether the data block is valid or invalid. The export cache and the state of each memory data block is used to determine whether a node should transmit a fetched data block to an initiator node in response to a read miss transaction. In this manner, the bus traffic is reduced since only the valid copy of the requested data item is transmitted to the initiator node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.