Hexagonally symmetric integrated circuit cell
US6342420B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2000 |
| Grant date | Jan 29, 2002 |
| Priority date | — |
| Expiry date | Apr 3, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/905
Abstract
An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.