Single-chip architecture for shared-memory router
US6343072B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1997 |
| Grant date | Jan 29, 2002 |
| Priority date | — |
| Expiry date | Dec 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3018
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention provides a single-chip method. The method includes a memory shared among packet buffers for receiving packets, packet buffers for transmitting packets, and packet header buffers for packet forwarding lookup. Accesses to that shared memory are multiplexed and prioritized. Packet reception is performed with relatively high priority, packet transmission is performed with medium priority, and packet forwarding lookup is performed with relatively low priority. The single-chip method includes circuits for serially receiving packet header information, converting that information into a parallel format for transmission to an SRAM for lookup, and queuing input packets for later forwarding at an output port. Similarly, the single-chip method includes circuits for queuing output packets for transmission at an output port, receiving packet forwarding information from the SRAM in a parallel format, and converting packet header information from output packets into a serial format for transmission. The single-chip method also includes a region in its shared memory for a packet forwarding table, and circuits for performing forwarding lookup responsive to packet header information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.