Method for forming pillar CMOS
US6344381B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2000 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | May 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end. A gate insulator dioxide is formed over both sides of the pillar and gate electrodes are formed over the gate insulators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.