Method for forming a semiconductor device
US6344413B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1998 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Feb 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/891
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for forming a semiconductor device having an capacitor, where the capacitor is in-laid in a cavity formed in the semiconductor substrate and part of a high density memory. One embodiment first forms a bottom electrode in the cavity and then fills the cavity with a sacrificial layer to allow chemical mechanical polishing (CMP) of at least one of the capacitor electrodes. After removing portions of the bottom electrode and portions of the sacrificial layer, a dielectric layer is formed. A top electrode is then formed over the dielectric layer. The dielectric layer so formed isolates the bottom electrode from the top electrode preventing shorting and leakage currents. In one embodiment, a single top electrode layer is formed for multiple bottom electrodes, reducing the complexity of the memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.