Chip size package semiconductor device and method of forming the same
US6344696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1998 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Oct 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor chip having a bonding face to be mounted onto a mother board, wherein a low elastic modulus resin layer is provided in contact directly with the bonding face of the semiconductor chip without intervening any interposer to form a chip size package, and the low elastic modulus resin layer has at least a conductive pattern of a build-up type, and wherein the low elastic modulus resin layer has both a sufficiently low elastic modulus and a sufficiently large thickness for allowing realization of a stress caused due to a difference in thermal expansion coefficient between the semiconductor chip and the mother board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.