Data communications device and associated method for arbitrating access using dynamically programmable arbitration scheme and limits on data transfers
US6345345B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1999 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Jan 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data communications device and method for arbitrating access to a system memory of the communications device via a peripheral component interconnect (PCI) bus in a network interface having a memory management unit for managing transmit data transfers from the system memory to a transmit buffer memory, and receive data transfers from a receive buffer memory to the system memory. The memory management unit includes an arbitration block having an arbiter state machine, which receives requests for access to the PCI bus in order to provide the transmission and reception of data, descriptors and status information. The arbiter state machine grants the PCI bus access to a request having a higher priority in accordance with a preset priority scheme. The memory management unit has a transmit transfer control register and a receive transfer control register containing programmable values that limit the maximum number of transmit data transfers and receive data transfers allowed within a single PCI bus mastership period. Also, the transmit and receive transfer control registers contain programmable values that limit the number of allowed transmit data transfers within a single PCI bus masters…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.